/* Copyright (c) 2015, The Linux Foundation. All rights reserved.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 and
 * only version 2 as published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 */

#ifndef __MSM_CLOCKS_HWIO_FSM9010_H
#define __MSM_CLOCKS_HWIO_FSM9010_H

#define GPLL0_MODE			0x0000
#define GPLL0_L				0x0004
#define GPLL0_M				0x0008
#define GPLL0_N				0x000C
#define GPLL0_USER_CTL			0x0010
#define GPLL0_CONFIG_CTL		0x0014
#define GPLL0_TEST_CTL			0x0018
#define GPLL0_STATUS			0x001C
#define GPLL1_MODE			0x0040
#define GPLL1_L				0x0044
#define GPLL1_M				0x0048
#define GPLL1_N				0x004C
#define GPLL1_USER_CTL			0x0050
#define GPLL1_CONFIG_CTL		0x0054
#define GPLL1_TEST_CTL			0x0058
#define GPLL1_STATUS			0x005C
#define GPLL2_MODE			0x0080
#define GPLL2_L				0x0084
#define GPLL2_M				0x0088
#define GPLL2_N				0x008C
#define GPLL2_USER_CTL			0x0090
#define GPLL2_CONFIG_CTL		0x0094
#define GPLL2_TEST_CTL			0x0098
#define GPLL2_STATUS			0x009C
#define GPLL3_MODE			0x00C0
#define GPLL3_L				0x00C4
#define GPLL3_M				0x00C8
#define GPLL3_N				0x00CC
#define GPLL3_USER_CTL			0x00D0
#define GPLL3_CONFIG_CTL		0x00D4
#define GPLL3_TEST_CTL			0x00D8
#define GPLL3_STATUS			0x00DC
#define USB30_MASTER_CBCR		0x0240
#define USB30_SLEEP_CBCR		0x0244
#define USB30_MOCK_UTMI_CBCR		0x0248
#define USB30_MASTER_CMD_RCGR		0x024C
#define USB30_MASTER_CFG_RCGR		0x0250
#define USB30_MASTER_M			0x0254
#define USB30_MASTER_N			0x0258
#define USB30_MASTER_D			0x025C
#define USB30_MOCK_UTMI_CMD_RCGR	0x0260
#define USB30_MOCK_UTMI_CFG_RCGR	0x0264
#define USB_30_BCR			0x0274
#define SYS_NOC_USB3_AXI_CBCR		0x0278
#define USB3_PHY_BCR			0x0280
#define USB3PHY_PHY_BCR			0x0284
#define USB3_PHY_AUX_CBCR		0x0288
#define USB3_PHY_PIPE_CBCR		0x028C
#define USB3_PHY_PIPE_MISC		0x0290
#define USB3_PHY_AUX_CMD_RCGR		0x0294
#define USB3_PHY_AUX_CFG_RCGR		0x0298
#define USB_HS_HSIC_BCR			0x03C0
#define USB_HS_HSIC_GDSCR		0x03C4
#define USB_HSIC_AHB_CBCR		0x03C8
#define USB_HSIC_SYSTEM_CMD_RCGR	0x03CC
#define USB_HSIC_SYSTEM_CFG_RCGR	0x03D0
#define USB_HSIC_SYSTEM_CBCR		0x03E0
#define USB_HSIC_CMD_RCGR		0x03E4
#define USB_HSIC_CFG_RCGR		0x03E8
#define USB_HSIC_CBCR			0x03F8
#define USB_HSIC_IO_CAL_CMD_RCGR	0x0400
#define USB_HSIC_IO_CAL_CFG_RCGR	0x0404
#define USB_HSIC_IO_CAL_CBCR		0x0414
#define USB_HSIC_IO_CAL_SLEEP_CBCR	0x0418
#define USB_HS_BCR			0x0480
#define USB_HS_SYSTEM_CBCR		0x0484
#define USB_HS_AHB_CBCR			0x0488
#define USB_HS_INACTIVITY_TIMERS_CBCR   0x048C
#define USB_HS_SYSTEM_CMD_RCGR		0x0490
#define USB_HS_SYSTEM_CFG_RCGR		0x0494
#define USB2A_PHY_BCR			0x04A8
#define USB2A_PHY_SLEEP_CBCR		0x04AC
#define USB2_HS_PHY_ONLY_BCR		0x04B0
#define SDCC1_BCR			0x04C0
#define SDCC1_APPS_CBCR			0x04C4
#define SDCC1_AHB_CBCR			0x04C8
#define SDCC1_INACTIVITY_TIMERS_CBCR    0x04CC
#define SDCC1_APPS_CMD_RCGR		0x04D0
#define SDCC1_APPS_CFG_RCGR		0x04D4
#define SDCC1_APPS_M			0x04D8
#define SDCC1_APPS_N			0x04DC
#define SDCC1_APPS_D			0x04E0
#define BLSP1_BCR			0x05C0
#define BLSP1_AHB_CBCR			0x05C4
#define BLSP1_SLEEP_CBCR		0x05C8
#define BLSP_UART_SIM_CMD_RCGR		0x0600
#define BLSP_UART_SIM_CFG_RCGR		0x0604
#define BLSP1_QUP1_BCR			0x0640
#define BLSP1_QUP1_SPI_APPS_CBCR	0x0644
#define BLSP1_QUP1_I2C_APPS_CBCR	0x0648
#define BLSP1_QUP1_SPI_APPS_CMD_RCGR    0x064C
#define BLSP1_QUP1_SPI_APPS_CFG_RCGR    0x0650
#define BLSP1_QUP1_SPI_APPS_M		0x0654
#define BLSP1_QUP1_SPI_APPS_N		0x0658
#define BLSP1_QUP1_SPI_APPS_D		0x065C
#define BLSP1_QUP1_I2C_APPS_CMD_RCGR    0x0660
#define BLSP1_QUP1_I2C_APPS_CFG_RCGR    0x0664
#define BLSP1_UART1_BCR			0x0680
#define BLSP1_UART1_APPS_CBCR		0x0684
#define BLSP1_UART1_SIM_CBCR		0x0688
#define BLSP1_UART1_APPS_CMD_RCGR	0x068C
#define BLSP1_UART1_APPS_CFG_RCGR	0x0690
#define BLSP1_UART1_APPS_M		0x0694
#define BLSP1_UART1_APPS_N		0x0698
#define BLSP1_UART1_APPS_D		0x069C
#define BLSP1_QUP2_BCR			0x06C0
#define BLSP1_QUP2_SPI_APPS_CBCR	0x06C4
#define BLSP1_QUP2_I2C_APPS_CBCR	0x06C8
#define BLSP1_QUP2_SPI_APPS_CMD_RCGR    0x06CC
#define BLSP1_QUP2_SPI_APPS_CFG_RCGR    0x06D0
#define BLSP1_QUP2_SPI_APPS_M		0x06D4
#define BLSP1_QUP2_SPI_APPS_N		0x06D8
#define BLSP1_QUP2_SPI_APPS_D		0x06DC
#define BLSP1_QUP2_I2C_APPS_CMD_RCGR    0x06E0
#define BLSP1_QUP2_I2C_APPS_CFG_RCGR    0x06E4
#define BLSP1_UART2_BCR			0x0700
#define BLSP1_UART2_APPS_CBCR		0x0704
#define BLSP1_UART2_SIM_CBCR		0x0708
#define BLSP1_UART2_APPS_CMD_RCGR	0x070C
#define BLSP1_UART2_APPS_CFG_RCGR	0x0710
#define BLSP1_UART2_APPS_M		0x0714
#define BLSP1_UART2_APPS_N		0x0718
#define BLSP1_UART2_APPS_D		0x071C
#define BLSP1_QUP3_BCR			0x0740
#define BLSP1_QUP3_SPI_APPS_CBCR	0x0744
#define BLSP1_QUP3_I2C_APPS_CBCR	0x0748
#define BLSP1_QUP3_SPI_APPS_CMD_RCGR    0x074C
#define BLSP1_QUP3_SPI_APPS_CFG_RCGR    0x0750
#define BLSP1_QUP3_SPI_APPS_M		0x0754
#define BLSP1_QUP3_SPI_APPS_N		0x0758
#define BLSP1_QUP3_SPI_APPS_D		0x075C
#define BLSP1_QUP3_I2C_APPS_CMD_RCGR    0x0760
#define BLSP1_QUP3_I2C_APPS_CFG_RCGR    0x0764
#define BLSP1_UART3_BCR			0x0780
#define BLSP1_UART3_APPS_CBCR		0x0784
#define BLSP1_UART3_SIM_CBCR		0x0788
#define BLSP1_UART3_APPS_CMD_RCGR	0x078C
#define BLSP1_UART3_APPS_CFG_RCGR	0x0790
#define BLSP1_UART3_APPS_M		0x0794
#define BLSP1_UART3_APPS_N		0x0798
#define BLSP1_UART3_APPS_D		0x079C
#define BLSP1_QUP4_BCR			0x07C0
#define BLSP1_QUP4_SPI_APPS_CBCR	0x07C4
#define BLSP1_QUP4_I2C_APPS_CBCR	0x07C8
#define BLSP1_QUP4_SPI_APPS_CMD_RCGR    0x07CC
#define BLSP1_QUP4_SPI_APPS_CFG_RCGR    0x07D0
#define BLSP1_QUP4_SPI_APPS_M		0x07D4
#define BLSP1_QUP4_SPI_APPS_N		0x07D8
#define BLSP1_QUP4_SPI_APPS_D		0x07DC
#define BLSP1_QUP4_I2C_APPS_CMD_RCGR    0x07E0
#define BLSP1_QUP4_I2C_APPS_CFG_RCGR    0x07E4
#define BLSP1_UART4_BCR			0x0800
#define BLSP1_UART4_APPS_CBCR		0x0804
#define BLSP1_UART4_SIM_CBCR		0x0808
#define BLSP1_UART4_APPS_CMD_RCGR	0x080C
#define BLSP1_UART4_APPS_CFG_RCGR	0x0810
#define BLSP1_UART4_APPS_M		0x0814
#define BLSP1_UART4_APPS_N		0x0818
#define BLSP1_UART4_APPS_D		0x081C
#define PDM2_BCR			0x0CC0
#define PDM2_AHB_CBCR			0x0CC4
#define PDM2_XO4_CBCR			0x0CC8
#define PDM2_CBCR			0x0CCC
#define PDM2_CMD_RCGR			0x0CD0
#define PDM2_CFG_RCGR			0x0CD4
#define PRNG_BCR			0x0D00
#define PRNG_AHB_CBCR			0x0D04
#define TCSR_BCR			0x0DC0
#define TCSR_AHB_CBCR			0x0DC4
#define BOOT_ROM_BCR			0x0E00
#define BOOT_ROM_AHB_CBCR		0x0E04
#define MSG_RAM_BCR			0x0E40
#define MSG_RAM_AHB_CBCR		0x0E44
#define TLMM_BCR			0x0E80
#define TLMM_AHB_CBCR			0x0E84
#define TLMM_CBCR			0x0E88
#define MPM_BCR				0x0EC0
#define MPM_MISC			0x0EC4
#define MPM_AHB_CBCR			0x0EC8
#define ACC_CMD_RCGR			0x0F80
#define ACC_CFG_RCGR			0x0F84
#define ACC_MISC			0x0F94
#define SPMI_BCR			0x0FC0
#define SPMI_SER_CBCR			0x0FC4
#define SPMI_CNOC_AHB_CBCR		0x0FC8
#define SPMI_AHB_CBCR			0x0FCC
#define SPMI_SER_CMD_RCGR		0x0FD0
#define SPMI_SER_CFG_RCGR		0x0FD4
#define SPMI_AHB_CMD_RCGR		0x0FE8
#define SPMI_AHB_CFG_RCGR		0x0FEC
#define SPDM_BCR			0x1000
#define SPDM_CFG_AHB_CBCR		0x1004
#define SPDM_MSTR_AHB_CBCR		0x1008
#define SPDM_FF_CBCR			0x100C
#define SPDM_BIMC_CY_CBCR		0x1010
#define SPDM_SNOC_CY_CBCR		0x1014
#define SPDM_DEBUG_CY_CBCR		0x1018
#define SPDM_PNOC_CY_CBCR		0x101C
#define SPDM_RPM_CY_CBCR		0x1020
#define CE1_BCR				0x1040
#define CE1_CBCR			0x1044
#define CE1_AXI_CBCR			0x1048
#define CE1_AHB_CBCR			0x104C
#define CE1_CMD_RCGR			0x1050
#define CE1_CFG_RCGR			0x1054
#define CE2_BCR				0x1080
#define CE2_CBCR			0x1084
#define CE2_AXI_CBCR			0x1088
#define CE2_AHB_CBCR			0x108C
#define CE2_CMD_RCGR			0x1090
#define GCC_XO_DIV4_CBCR	        0x10C8
#define CE2_CFG_RCGR			0x1094
#define APSS_AHB_CBCR			0x1204
#define APSS_AXI_CBCR			0x1208
#define APSS_AHB_CMD_RCGR		0x120C
#define APSS_AHB_CFG_RCGR		0x1210
#define APSS_AHB_MISC			0x1220
#define APCS_GPLL_ENA_VOTE		0x1480
#define APCS_CLOCK_BRANCH_ENA_VOTE	0x1484
#define APCS_CLOCK_SLEEP_ENA_VOTE	0x1488
#define SPARE_GPLL_ENA_VOTE		0x15C0
#define SPARE_CLOCK_BRANCH_ENA_VOTE	0x15C4
#define WDOG_DEBUG			0x1780
#define FLUSH_ETR_DEBUG_TIMER		0x1784
#define STOP_CAPTURE_DEBUG_TIMER	0x1788
#define SW_SRST				0x1800
#define GCC_DEBUG_CLK_CTL		0x1880
#define CLOCK_FRQ_MEASURE_CTL		0x1884
#define CLOCK_FRQ_MEASURE_STATUS	0x1888
#define GCC_PLLTEST_PAD_CFG		0x188C
#define GCC_GP1_CBCR			0x1900
#define GCC_GP1_CMD_RCGR		0x1904
#define GCC_GP1_CFG_RCGR		0x1908
#define GCC_GP1_M			0x190C
#define GCC_GP1_N			0x1910
#define GCC_GP1_D			0x1914
#define GCC_GP2_CBCR			0x1940
#define GCC_GP2_CMD_RCGR		0x1944
#define GCC_GP2_CFG_RCGR		0x1948
#define GCC_GP2_M			0x194C
#define GCC_GP2_N			0x1950
#define GCC_GP2_D			0x1954
#define GCC_GP3_CBCR			0x1980
#define GCC_GP3_CMD_RCGR		0x1984
#define GCC_GP3_CFG_RCGR		0x1988
#define GCC_GP3_M			0x198C
#define GCC_GP3_N			0x1990
#define GCC_GP3_D			0x1994
#define APSS_BOOT_CLOCK_CTL		0x19C0
#define USB_BOOT_CLOCK_CTL		0x1A00
#define PCIE_0_BCR			0x1AC0
#define PCIE_0_GDSCR			0x1AC4
#define PCIE_0_LINK_DOWN_BCR		0x1AC8
#define PCIE_0_PHY_BCR			0x1B00
#define PCIE_0_SLV_AXI_CBCR		0x1B04
#define PCIE_0_MSTR_AXI_CBCR		0x1B08
#define PCIE_0_CFG_AHB_CBCR		0x1B0C
#define PCIE_0_AUX_CBCR			0x1B10
#define PCIE_0_PIPE_CBCR		0x1B14
#define PCIE_0_PIPE_CMD_RCGR		0x1B18
#define PCIE_0_PIPE_CFG_RCGR		0x1B1C
#define PCIEPHY_0_PHY_BCR		0x1B24
#define PCIE_0_MISC_RESET		0x1B28
#define PCIE_0_AUX_CMD_RCGR		0x1B2C
#define PCIE_0_AUX_CFG_RCGR		0x1B30
#define PCIE_0_AUX_M			0x1B34
#define PCIE_0_AUX_N			0x1B38
#define PCIE_0_AUX_D			0x1B3C
#define PCIE_1_BCR			0x1B40
#define PCIE_1_GDSCR			0x1B44
#define PCIE_1_LINK_DOWN_BCR		0x1B48
#define PCIE_1_PHY_BCR			0x1B80
#define PCIE_1_SLV_AXI_CBCR		0x1B84
#define PCIE_1_MSTR_AXI_CBCR		0x1B88
#define PCIE_1_CFG_AHB_CBCR		0x1B8C
#define PCIE_1_AUX_CBCR			0x1B90
#define PCIE_1_PIPE_CBCR		0x1B94
#define PCIE_1_PIPE_CMD_RCGR		0x1B98
#define PCIE_1_PIPE_CFG_RCGR		0x1B9C
#define PCIEPHY_1_PHY_BCR		0x1BA0
#define PCIE_1_MISC_RESET		0x1BA8
#define PCIE_1_AUX_CMD_RCGR		0x1BAC
#define PCIE_1_AUX_CFG_RCGR		0x1BB0
#define PCIE_1_AUX_M			0x1BB4
#define PCIE_1_AUX_N			0x1BB8
#define PCIE_1_AUX_D			0x1BBC
#define GPLL4_MODE			0x1DC0
#define GPLL4_L_VAL			0x1DC4
#define GPLL4_M_VAL			0x1DC8
#define GPLL4_N_VAL			0x1DCC
#define GPLL4_USER_CTL			0x1DD0
#define GPLL4_CONFIG_CTL		0x1DD4
#define GPLL4_TEST_CTL			0x1DD8
#define GPLL4_STATUS			0x1DDC
#define PCIE_0_PHY_LDO_EN		0x1E00
#define PCIE_1_PHY_LDO_EN		0x1E04
#define GCC_SPARE0_REG			0x1F40
#define GCC_SPARE1_REG			0x1F80
#define RAW_SLEEP_CLK_CTRL		0x1FC0
#define MPLL5_MODE			0x2000
#define MPLL5_L_VAL			0x2004
#define MPLL5_M_VAL			0x2008
#define MPLL5_N_VAL			0x200C
#define MPLL5_USER_CTL			0x2010
#define MPLL5_CONFIG_CTL		0x2014
#define MPLL5_TEST_CTL			0x2018
#define MPLL5_STATUS			0x201C
#define MPLL6_MODE			0x2040
#define MPLL6_L_VAL			0x2044
#define MPLL6_M_VAL			0x2048
#define MPLL6_N_VAL			0x204C
#define MPLL6_USER_CTL			0x2050
#define MPLL6_CONFIG_CTL		0x2054
#define MPLL6_TEST_CTL			0x2058
#define MPLL6_STATUS			0x205C
#define GPLL7_MODE			0x2080
#define GPLL7_L_VAL			0x2084
#define GPLL7_M_VAL			0x2088
#define GPLL7_N_VAL			0x208C
#define GPLL7_USER_CTL			0x2090
#define GPLL7_CONFIG_CTL		0x2094
#define GPLL7_TEST_CTL			0x2098
#define GPLL7_STATUS			0x209C
#define MPLL9_MODE			0x2100
#define MPLL9_L_VAL			0x2104
#define MPLL9_M_VAL			0x2108
#define MPLL9_N_VAL			0x210C
#define MPLL9_USER_CTL			0x2110
#define MPLL9_CONFIG_CTL		0x2114
#define MPLL9_TEST_CTL			0x2118
#define MPLL9_STATUS			0x211C
#define MPLL10_MODE			0x2140
#define MPLL10_L_VAL			0x2144
#define MPLL10_M_VAL			0x2148
#define MPLL10_N_VAL			0x214C
#define MPLL10_USER_CTL			0x2150
#define MPLL10_CONFIG_CTL		0x2154
#define MPLL10_TEST_CTL			0x2158
#define MPLL10_STATUS			0x215C
#define CE_AHB_CMD_RCGR			0x2384
#define CE_AHB_CFG_RCGR			0x2388
#define DESC_IMEM_BCR			0x23C0
#define DESC_IMEM_AXI_CBCR		0x23C4
#define DESC_IMEM_CFG_AHB_CBCR		0x23C8
#define PDM1_BCR			0x2980
#define PDM1_AHB_CBCR			0x2984
#define PDM1_XO4_CBCR			0x2988
#define PDM1_CBCR			0x298C
#define RBCPR_Q6_BCR			0x3D40
#define RBCPR_Q6_CBCR			0x3D44
#define RBCPR_Q6_AHB_CBCR		0x3D48
#define RBCPR_Q6_CMD_RCGR		0x3D4C
#define RBCPR_Q6_CFG_RCGR		0x3D50
#define GMAC1_AXI_CMD_RCGR		0x3D80
#define GMAC1_AXI_CFG_RCGR		0x3D84
#define GMAC1_AXI_M			0x3D88
#define GMAC1_AXI_N			0x3D8C
#define GMAC1_AXI_D			0x3D90
#define GMAC2_AXI_CMD_RCGR		0x3D94
#define GMAC2_AXI_CFG_RCGR		0x3D98
#define GMAC2_AXI_M			0x3D9C
#define GMAC2_AXI_N			0x3DA0
#define GMAC2_AXI_D			0x3DA4
#define GMAC1_AXI_CBCR			0x3DA8
#define GMAC2_AXI_CBCR			0x3DAC
#define GMAC1_BCR			0x3DB0
#define GMAC2_BCR			0x3DB4
#define GMAC_PTP_AUXREF_CMD_RCGR	0x3DC0
#define GMAC_PTP_AUXREF_CFG_RCGR	0x3DC4
#define GMAC_PTP_AUXREF_M		0x3DC8
#define GMAC_PTP_AUXREF_N		0x3DCC
#define GMAC_PTP_AUXREF_D		0x3DD0
#define GMAC_PTP_AUXREF_CBCR		0x3DD4
#define SDCC1_CDCCAL_SLEEP_CBCR		0x3E40
#define SDCC1_CDCCAL_FF_CBCR		0x3E44
#define SDCC1_MISC			0x3E48
#define BIMC_APSS_AXI_CMD_RCGR		0x3E80
#define BIMC_APSS_AXI_CFG_RCGR		0x3E84
#define USB_HS_PHY_CFG_AHB_CBCR		0x3EC0
#define SGMII_01_PHY_CFG_AHB_CBCR	0x3EC4
#define RGMII_CDC_DLY_CFG_AHB_CBCR	0x3EC8
#define USB_SS_PHY_LDO_EN		0x3F00
#define GCC_SPARE2_REG			0x3F80
#define GCC_SPARE3_REG			0x3FC0

#endif
